Modern wireless communication systems employ large bandwidth digital modulated signals with very high peak-to-average power ratio (PAPR) to enhance spectral efficiency and maximize the data rate. However, high PAPR digital modulations schemes are strongly detrimental for the radiofrequency (RF) amplifier that must operate most of the time several dB in back-off with respect to the nominal power and, therefore, with very low efficiency.
A common technique to improve the RF high power amplifier (HPA) efficiency is envelope tracking (ET), which implements a dynamic bias supply that follows a set point proportional to the RF input signal envelope, in order to maintain the RF HPA much closer to the more efficient full power operating condition. The concept is to drain and handle less energy from the supply when low power has to be delivered to the load; however, the efficiency of the supply power converter becomes similarly important for the overall efficiency of the ET transmitter. Moreover, since the HPA gain varies with the bias, typically ET must be used in combination with digital predistortion (DPD) to recover linear amplification. Therefore, in ET architectures the supply modulator (or envelope amplifier) must have the highest possible conversion efficiency with very demanding specification in terms of bandwidth and full power dynamics (slew rates), while generating only distortion components that can be easily controlled and eliminated.
The proposed ET architecture is a multilevel power converter based on direct digital-to-analog conversion of three isolated dc-voltages with binary coded magnitudes, so that eight different output voltage levels are generated, depending on the state of three cascaded single-pole double-through switches (3 legs). The isolated digital signals that control the legs comes directly from the transmitter baseband field programmable gate array (FPGA) that, knowing the power that the final HPA has to transmit, decides the supply voltage that maximizes its efficiency and predistorts the RF-input to maintain linearity. There is no need of closing problematic feedback loops if accurate time alignment between variable DC-supply (drain) and predistorted RF-input (gate) is provided to the HPA. Each leg is composed by two fast Gallium Nitride (GaN) on silicon semiconductor power switches, ball grid array (BGA) soldered in an extremely compact circuit layout with tight control of parasitic elements, which guarantees low commutation losses even at the high operating frequencies related to the envelope.
This digital-to-analog power conversion implemented by the circuit makes the proposed supply modulator a power digital-to-analog converter "power-DAC". The circuit is able to commutate between any of the eight possible output states in few nanoseconds, which are compatible with the ET of modulated signals up to 80 MHz of bandwidth with power peaks of few tens of watts. The efficiency varies from 80% to 95% and the induced distortion produced from voltage supply commutations proved to be under control and plainly recoverable with DPD.
The power-DAC has been successfully used also in radar application in order to improve the efficiency when advanced chirp signals with spectral confinement (RF-pulse with special time windowing functions) are adopted.
Other possible power-DAC applications are those where any pulse of programmable shape must be generated to drive devices like LEDs or mechanical actuators: pulse-width modulation (PWM), discrete pulse-amplitude modulation (PAM) and pulse-position modulation (PPM) are all viable feeding waveforms with the benefits of large output power and bandwidth of the power-DAC.
More details in: "Envelope Tracking of an RF High Power Amplifier with an 8-level Digitally Controlled GaN-on-Si Supply Modulator", C. Florian, T. Cappello, R.P. Paganelli, D. Niessen, F. Filicori, IEEE Transaction on Microwave Theory and Techniques, Vol. 63, NO. 8, August 2015.
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