Fabrication process of a trench gate power MOS transistor with scaled channel (Brevetto)

Type

• Brevetto (Classe)
• Brevetto (Classe)
• Prodotto della ricerca (Classe)

Label

• Fabrication process of a trench gate power MOS transistor with scaled channel (Brevetto) (literal)

Anno

• 2005-01-01T00:00:00+01:00 (literal)

Alternative label

• Currò G. ; Fazio B. (2005)
  Fabrication process of a trench gate power MOS transistor with scaled channel
  
  (literal)

Titolo

• Fabrication process of a trench gate power MOS transistor with scaled channel (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori

• Currò G. ; Fazio B. (literal)

Http://www.cnr.it/ontology/cnr/brevetti.owl#ricaduteEconomicheOccupazionali

• Ricadute economiche (literal)

Http://www.cnr.it/ontology/cnr/brevetti.owl#settoreMerceologicoISTAT

• Ricerca e sviluppo industriale (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#proprieta

• STMicroelectronics S.r,l., Agrate Brianza (IT) (literal)

Http://www.cnr.it/ontology/cnr/brevetti.owl#tipoDiBrevetto

• Internazionale (literal)

Numero brevetto

• US 6,887,760 B2 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#descrizioneSinteticaDelProdotto

• A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized. Source regions are formed by implanting dopants in the body region while using the oxidized edge surfaces as a selfaligned mask, and the implanted dopants are diffused in the body region. (literal)

Anno di deposito

• 2005 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni

• 1) Messina (Italy) 2) Messina (Italy) (literal)

Titolo

• Fabrication process of a trench gate power MOS transistor with scaled channel (literal)

Http://www.cnr.it/ontology/cnr/brevetti.owl#trasferimentoBrevetto

• Trasferimento previsto a breve (literal)

Prodotto di

• Institute for chemical and physical processes (IPCF) (Istituto)

Autore CNR

• BARBARA FAZIO (Persona)

Incoming links:

Prodotto

• Institute for chemical and physical processes (IPCF) (Istituto)

Autore CNR di

• BARBARA FAZIO (Persona)