Consiglio Nazionale delle Ricerche

Tipo di prodottoContributo in atti di convegno
TitoloEmbedded ECC Solutions for emerging memories (PCMs)
Anno di pubblicazione2016
FormatoElettronico
Autore/iM. Ferrari, A. Tomasoni, S. Bellini, P. Amato, M. Sforzin, C. Laurent
Affiliazioni autoriIEIIT, Consiglio Nazionale delle Ricerche, Via Ponzio 34/5, 20133 Milano, Italy DEIB, Politecnico di Milano, P.za L. da Vinci, 20133 Milano, Italy Micron Semiconductor Italia s.r.l., Via Torri Bianche 24, 20871 Vimercate (MB), Italy
Autori CNR e affiliazioni
  • MARCO PIETRO FERRARI
  • ALESSANDRO TOMASONI
Lingua/e
  • inglese
AbstractEmerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAMlike and/or eXecuted-in-Place requirements of Storage Class Memory devices. The error correction capability would help manufacturers to cope with unknown failure mechanisms and to fulfill the market demand for a rapid increase in density. This paper shows the design of an ECC decoder for a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by pre-computing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated by the number of elementary gates to traverse, and by the total number of elementary gates of the decoder. Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than 250 000 umq. Index Terms--Error Correction Codes, Flash Memo
Lingua abstractinglese
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Verificato da refereeSì: Internazionale
Stato della pubblicazionePublished version
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Parole chiaveError Correction Codes, Flash Memories, DRAM, Emerging Memories, Storage Class Memories.
Link (URL, URI)https://kluedo.ub.uni-kl.de/files/4320/FINAL_W07.8.1.pdf
Titolo convegno/congressoEmerging Memory Workshop (colocated with DATE 2016)
Luogo convegno/congressoDresden, Germany
Data/e convegno/congresso18/3/2016
RilevanzaInternazionale
RelazioneContributo
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Strutture CNR
  • IEIIT — Istituto di elettronica e di ingegneria dell'informazione e delle telecomunicazioni
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