Consiglio Nazionale delle Ricerche

Tipo di prodottoContributo in atti di convegno
TitoloComputer-aided synthesis of a Bidimensional Discrete Cosine Transform chip
Anno di pubblicazione1989
  • Elettronico
  • Cartaceo
Autore/iV. Rampa, G. De Micheli
Affiliazioni autoriCSTS-CNR, c/o Politecnico di Milano, Milano; CSL, Stanford University, Stanford
Autori CNR e affiliazioni
  • inglese
AbstractThe design of an integrated circuit implementing a bidimensional discrete cosine transform (BDCT) is presented. Such a circuit can be used to remove redundancy of video information in low-rate transmission channels and to perform video compression for image storage. The chip architecture is motivated by the fact that the BDCT equations can be solved row-by-row and column-by-column by a simpler monodimensional DCT (MDCT). Therefore, the chip structure is partitioned into three stages: the first and the last one implement MDCTs, while the second stage is a shared memory array. The DCT design was achieved by means of the OLYMPUS synthesis system, an experimental suite of synthesis tools. A parameterized behavioral description of the monodimensional DCT operator was specified in a high-level description language, HardwareC, in terms of concurrent processes communicating through a shared medium. The circuit layer was synthesized automatically from this description.
Lingua abstractinglese
Altro abstract-
Lingua altro abstract-
Pagine da220
Pagine a225
Pagine totali6
Numero volume della rivista-
Titolo del volumeProceedings of the IEEE International Symposium on Circuits and Systems 1989 (ISCAS'89)
Numero volume della serie/collana1
Curatore/i del volume-
  • IEEE - Institute of Electrical and Electronics Engineers, Piscataway, N.J. (Stati Uniti d'America)
Verificato da refereeSì: Internazionale
Stato della pubblicazione-
Indicizzazione (in banche dati controllate)
  • ISI Web of Science (WOS) (Codice:A1989BR31U00053)
  • IEEE Xplore digital library (Codice:100331)
Parole chiave-
Link (URL, URI)
Titolo convegno/congressoIEEE International Symposium on Circuits and Systems 1989 (ISCAS'89)
Luogo convegno/congressoPortland (USA)
Data/e convegno/congresso8-11 May
Titolo parallelo-
Note/Altre informazioniIDS Number: BR31U
Strutture CNR
  • IEIIT — Istituto di elettronica e di ingegneria dell'informazione e delle telecomunicazioni
Moduli CNR
    Progetti Europei-
    • Computer-aided synthesis of a Bidimensional Discrete Cosine Transform chip
      Descrizione: Published paper