Consiglio Nazionale delle Ricerche

Tipo di prodottoContributo in atti di convegno
TitoloDesign representation and manipulation for high-level synthesis of DSP algorithms
Anno di pubblicazione1992
Formato
  • Elettronico
  • Cartaceo
Autore/iA. Balboni, C. Costi, F. Fummi, M. Porta, V. Rampa, D. Sciuto
Affiliazioni autoriItaltel SIT, R&D Dept., Settimo Milanese; CEFRIEL, Milano; CSTS-CNR, Milano; Dipartimento di Automazione Industriale, Università di Brescia, Brescia
Autori CNR e affiliazioni
  • VITTORIO RAMPA
Lingua/e
  • inglese
AbstractPresents the new internal representation chosen for the high-level synthesis environment system under development at the Cefriel center. The aim of the work performed in Cefriel is to build a high-level synthesis environment constituted by a set of tools making it possible to perform synthesis of different classes of array architectures dedicated mainly to DSP (digital signal processing) applications. The basic representation to evaluate the best class of target architecture is a behavioral graph representation of the algorithm described in an HDL (hardware description language). This hierarchical representation and the algorithms that make it possible to manipulate it in order to identify the type of synthesis to be performed are discussed. The goal of the algorithms considered here is to modify the data flow graph and control flow graph in a way that will make easier the decision on the most suitable type of architecture to implement, given a specific algorithm and performance constraints. Structural synthesis can then be performed by the different modules of the environment. Orpheus, the systolic arrays synthesis module, is shown as an example.
Lingua abstractinglese
Altro abstract-
Lingua altro abstract-
Pagine da641
Pagine a644
Pagine totali4
Rivista-
Numero volume della rivista-
Serie/Collana-
Titolo del volumeProceedings of the IEEE International Symposium on Circuits and Systems 1992 (ISCAS'92)
Numero volume della serie/collana2
Curatore/i del volume-
ISBN0-7803-0593-0
DOI10.1109/ISCAS.1992.230170
Editore
  • IEEE - Institute of Electrical and Electronics Engineers, Piscataway, N.J. (Stati Uniti d'America)
Verificato da refereeSì: Internazionale
Stato della pubblicazione-
Indicizzazione (in banche dati controllate)
  • ISI Web of Science (WOS) (Codice:A1992BW69A00156)
  • IEEE Xplore digital library (Codice:230170)
Parole chiave-
Link (URL, URI)http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=230170
Titolo convegno/congressoIEEE International Symposium on Circuits and Systems 1992 (ISCAS'92)
Luogo convegno/congressoSan Diego
Data/e convegno/congressoMay 1992
RilevanzaInternazionale
RelazioneContributo
Titolo parallelo-
Note/Altre informazioniIDS Number: BW69A
Strutture CNR
  • IEIIT — Istituto di elettronica e di ingegneria dell'informazione e delle telecomunicazioni
Moduli CNR
    Progetti Europei-
    Allegati
    • Design representation and manipulation for high-level synthesis of DSP algorithms
      Descrizione: Published paper